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d ata s heet february 1995 o k i a s i c p r o d u c t s 0.8? mixed 3-v/5-v MSM38S0000 sea of gates and msm98s000 customer structured arrays
oki semiconductor reserves the right to make changes in specifications at anytime and without notice. this information furnished by oki semiconductor in this publication is believed to be accurate and reliable. however, no responsibility is assumed by oki semiconductor for its use; nor for any infringements of patents or other rights of third parties resulting from its use. no license is granted under any patents or patent rights of oki. oki semiconductor aix, dos, pc, and windows are trademarks, and ibm is a registered trademark of ibm corporation apollo, domain, and domainos are trademarks of apollo computer, a subsidiary of hewlett-packard autologic, idea, quickfault, quickgrade, quickpath, quicksim, and mentor graphics are trademarks of mentor graphics corporation composer, concept, hdl, leapfrog, pli, veritime, and vhdl are trademarks, and cadence, dracula, testscan, verifault, and verilog are registered trademarks of cadence design systems, inc. design compiler, hdl/vhdl compiler, test compiler, and vss are trademarks of synopsys, inc. hp and hp-ux are trademarks of hewlett-packard company alchemy and ikos are trademarks of ikos systems, inc. powerview, viewlogic, viewretargeter, viewsim, viewsynthesis, and workview are trademarks of viewlogic systems, inc. solaris, sun, sun-3, sun-4, and sunos are trademarks of sun microsystems, inc. unix is a registered trademark of unix system laboratories, inc. all other products or services mentioned in this document are identified by the trademarks, service marks, or product names as designated by the companies who market those products. inquiries concerning such trademarks should be made directly to those companies. t rademarks
1 oki semiconductor MSM38S0000/msm98s000 0.8? mixed 3-v/5-v sea of gates and customer structured arrays description oki? 0.8? asic products, specially designed for mixed 3-v/5-v applications, are now available in both sea of gates (sog) and customer structured array (csa) architectures. both the sog-based msm38s series and the csa-based msm98s series use a three-layer-metal process on 0.8? drawn (0.6? l-effec- tive) cmos technology. the semiconductor process is adapted from oki? production-proven 16-mbit dram manufacturing process. ideal for low-power portable applications, the msm38s/98s are constructed with separate power busses for internal core logic and configurable i/o functions. altogether, the architecture provides maximum flexibility, meeting the needs of all 3-v, 5-v, and mixed 3-v/5-v signal requirements. the msm38s sog series is available in seven sizes with up to 420 i/o pads and over 135,000 usable gates. sog array sizes are designed to fit the most popular quad flat pack (qfp) packages, such as 100-, 136-, 160-, and 208-pin qfps. msm38s sog-based designs are therefore ideal for pad-limited circuits that require rapid prototyping turnaround times. the msm98s csa series is an all-mask-level superset of the sog series, available in 29 sizes. the csa offerings combine the sog architecture? logic flexibility with the higher integration yielded by optimized diffusion for faster and more compact memory blocks. the msm98s is ideal for core-limited applications or circuits with large and/or multiple memory functions. customer modification to the structure of any of the 29 predefined masterslices, rather than creation of a new masterslice every time, improves the pro- totyping turnaround time over cell-based manufacturing techniques. both product families are supported by oki? proprietary memgen tool which quickly and easily gen- erates sog memories (for the msm38s) as well as optimized memories for the msm98s series. the fam- ilies also feature floorplanning to control pre-layout timing, clock-skew management software that guarantees worst-case clock skew of 1 ns or less, and scan-path design techniques that support atvg for fault coverage approaching 100%. features 0.8? drawn three-layer metal cmos mixed 3-v/5-v operation for low power and high speed sog and csa architecture availability clock tree cells with 1.0-ns clock skew, worst-case (fan-out = 2000 at 70 mhz) usable density from 6.5k to 135k gates i/os may be vss, 3 v, 5 v, vdd, cmos, ttl, and 3- state, with 2-ma to 48-ma drive i/o level shifter cells, allowing any buffer (input, output, or bidirectional) to interface with 3 v or 5 v slew-rate-controlled outputs for low radiated noise user-configurable single and multi-port memories specialized 3-v and 5-v macrocells, including phase- locked loop, and pci cells floorplanning for front-end simulation and back-end layout controls jtag boundary scan and scan-path atvg
n msm38s/98s data sheet n 2 oki semiconductor [1] row and column numbers are used to evaluate the number and size of mega macrocells that may be included into each array. for example, a 7,600-gate mega macrocell with a size and aspect ratio of 36 rows by 245 columns can be used on the msm98s032x032 or any larger array base, but not on the msm98s029x029. [2] usable gate count is design dependent and varies based upon the number of fan-outs per net, internal busses, floor plan, ram/rom blocks, etc. msm38s/98s family listing csa part # msm... sog part # msm... i/o pads rows [1] columns raw gates usable gates [2] 98s020x020 80 44 148 6,512 4,689 98s023x023 92 51 176 8,976 6,463 38s0110 100 56 194 10,752 7,741 98s026x026 104 59 200 11,800 8,496 98s029x029 116 66 228 15,048 10,835 98s032x032 128 74 252 18,648 13,427 38s0210 136 79 270 21,172 15,244 98s035x035 140 81 276 22,356 16,096 98s038x038 152 89 304 27,056 19,480 38s0300 160 94 322 30,080 21,658 98s041x041 164 96 328 31,488 22,671 98s044x044 176 104 356 37,024 25,917 98s047x047 188 111 380 42,180 29,526 98s050x050 200 119 408 48,552 33,986 98s053x053 212 126 432 54,432 38,102 38s0570 216 129 442 56,760 39,732 98s056x056 224 134 456 61,104 42,162 98s059x059 236 141 484 68,244 47,088 98s062x062 248 149 508 75,692 51,471 98s065x065 260 156 536 83,616 56,859 98s068x068 272 164 560 91,840 62,451 38s0980 280 169 580 97,344 66,194 98s071x071 284 171 588 100,548 67,367 98s074x074 296 179 612 109,548 72,302 98s077x077 308 186 636 118,296 75,709 98s080x080 320 194 664 128,816 82,442 98s083x083 332 201 688 138,288 88,504 98s086x086 38s1500 344 209 716 149,644 95,772 98s089x089 356 216 740 159,840 99,101 98s092x092 368 224 768 172,032 103,219 98s095x095 380 231 792 182,952 109,771 98s098x098 392 239 816 195,024 117,014 98s101x101 404 246 844 207,624 124,574 98s104x104 416 254 868 220,472 132,283 38s2250 420 256 880 224,256 134,554
n msm38s/98s data sheet n 3 oki semiconductor array architecture the primary components of a 0.8? msm38s/98s circuit include: i/o base cells configurable i/o pads for v dd , v ss , or i/o (i/o in both 3v and 5v) v dd and v ss pads dedicated to wafer probing separate power bus for output buffers separate power bus for internal core logic and input buffers core base cells containing n-channel and p-channel pairs, arranged in column of gates isolated gate structure for reduced input capacitance and increased routing flexibility each array has 16 dedicated corner pads for power and ground use during wafer probing, with four pads per corner. the arrays also have separate power rings for the internal core functions (v ddc and v ssc ) and output drive transistors (v ddo for 3 v and v sso ). figure 1. msm38s/98s array architecture msm98s000 csa layout methodology the procedure to design, place, and route a csa follows. 1. select suitable base array frame from the available predefined sizes. to select an array size: - identify the macrocell functions required and the minimum array size to hold the macrocell functions. four-transistor basic core cell separate power bus over i/o cell for output buffers (v ddo (3.3 v), v ddo (5 v), v sso ) v dd , v ss pads in each corner for wafer probing only congurable i/o pads for v dd (3.3 v), v dd (5 v), v ss , i/o (3.3 v), or i/o (5 v) separate power bus for internal core logic i/o cells include level shifter v sso v ddo (3.3 v) v ddo (5 v) column of gates core area v dd = 3.3 or 5 v
n msm38s/98s data sheet n 4 oki semiconductor - add together all the area occupied by the required random logic and macrocells and select the optimum array. 2. make a floor plan for the design? megacells. - oki design center engineers verify the master slice and review simulation. - oki design center engineers floorplan the array using oki? proprietary floorplanner and customer performance specifications. - using oki cad software, design center engineers remove the sog transistors and replace them with diffused memory macrocells to the customer? specifications. figure 2 shows an array base after placement of the optimized memory macrocells. figure 2. optimized memory macrocell floor plan 3. place and route logic into the array transistors. - oki design center engineers use layout software and customer performance specifications to connect the random logic and optimized memory macrocells. figure 3 marks the area in which placement and routing is performed with light shading. figure 3. random logic place and route mega macrocell early mask high-density rom high-density ram multi-port ram
n msm38s/98s data sheet n 5 oki semiconductor electrical characteristics [1] permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the other sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. [1] tr a , tf a ?ttl interface, normal input buffer. [2] tr b , tf b ?cmos interface, normal input buffer. [3] tr c , tf c ?ttl interface, schmitt trigger input buffer. [4] tr d , tf d ?cmos interface, schmitt trigger input buffer. [1] 50-mhz oscillator frequency for v dd is 4.5 ~ 5.5 v. absolute maximum ratings parameter symbol conditions [1] value unit power supply voltage v dd t j = 25?c v ss = 0 v -0.5 to +6.5 v input voltage v i -0.5 to v dd +0.5 v output voltage v o -0.5 to v dd +0.5 v output current per i/o base cell i o -24 to + 24 ma current per power pad i pad -90 to +90 ma storage temperature t stg -65 to +150 ?c recommended operating conditions (v ss = 0 v) parameter symbol rated value unit min typ max power supply voltage v dd 2.7 3.3 3.6 v 4.5 5.0 5.5 v operating temperature t a -40 +25 +85 ? input rise/fall time (normal type) [1][2] tr a , tf a 2 500 ns tr b , tf b 2 500 ns input rise/fall time (schmitt trigger type) [3][4] tr c , tf c 60 ? tr d , tf d 200 ? operating range (v ss = 0 v) parameter symbol rated value unit supply voltage v dd 2.7 to 5.5 v ambient temperature t a -40 to +85 ?c oscillation frequency [1] f osc 30 k to 50 m hz
n msm38s/98s data sheet n 6 oki semiconductor [1] typical condition is v dd = 5.0 v and t j = 25?c for a typical process. [2] ram/rom should be in power-down mode. dc characteristics (v dd = 4.5 ~ 5.5 v, v ss = 0 v, t j = -40?c ~ +85?c) parameter symbol conditions rated value unit min typ [1] max high-level input voltage v ih ttl input 2.2 v dd +0.5 v cmos input 0.7xv dd v dd +0.5 v low-level input voltage v il ttl input -0.5 0.8 v cmos input -0.5 0.3xv dd v ttl-level schmitt trigger input threshold voltage v t+ 1.7 2.2 v v t- 0.8 1.3 v d vt v t+ - v t- 0.2 0.4 v cmos-level schmitt trigger input threshold voltage v t+ 3.1 0.76xv dd v v t- 0.24xv dd 1.8 v d vt v t+ - v t- 0.6 1.3 v high-level output voltage v oh i oh = 2, 4, 8, 12, 16, 24 ma 3.7 v low-level output voltage v ol i ol = 2, 4, 8, 12, 16, 24 ma 0.4 v i ol = 48 ma 0.5 v high-level input current i ih v ih = v dd 0.01 10 ? v ih = v dd (50 k w pull down) 20 100 250 ? low-level input current i il v il = v ss -10 -0.01 ? v il = v ss (50 k w pull up) -250 -100 -20 ? v il = v ss (3 k w pull up) -5 -1.6 -0.5 ma 3-state output leakage current ioz h v oh = v dd 0.01 10 ? ioz l v ol = v ss -10 -0.01 ? v ol = v ss (50 k w pull up) -250 -100 -20 ? v ol = v ss (3 k w pull up) -5 -1.6 -0.5 ma stand-by current [2] i dds output open v ih = v dd , v il = v ss 0.1 100 ?
n msm38s/98s data sheet n 7 oki semiconductor [1] typical condition is v dd = 3.3 v and t j = 25?c for a typical process. [2] ram/rom should be in power-down mode. dc characteristics (v dd = 2.7 ~ 3.6 v, v ss = 0 v, t j = -40?c ~ +85?c) parameter symbol conditions rated value unit min typ [1] max high-level input voltage v ih cmos input 0.7xv dd v dd +0.5 v low-level input voltage v il cmos input -0.5 0.3xv dd v cmos-level schmitt trigger input threshold voltage v t+ 2 0.76xv dd v v t- 0.24xv dd 1 v d vt v t+ - v t- 0.1xv dd 1 v high-level output voltage v oh i oh = 1, 2, 4, 6, 8, 12 ma 2.2 v low-level output voltage v ol i ol = 1, 2, 4, 6, 8, 12, 24 ma 0.4 v high-level input current i ih v ih = v dd 0.01 1 ? v ih = v dd (100 k w pull down) 5 35 120 ? low-level input current i il v il = v ss -1 -0.01 ? v il = v ss (100 k w pull up) -120 -35 -5 ? v il = v ss (6 k w pull up) -2 -.55 -.120 ma 3-state output leakage current ioz h v oh = v dd 0.01 1 ? ioz l v ol = v ss -1 -0.01 ? v ol = v ss (100 k w pull up) -120 -35 -5 ? v ol = v ss (6 k w pull up) -2 -.55 -.12 ma stand-by current [2] i dds output open v ih = v dd , v il = v ss 0.1 10 ?
n msm38s/98s data sheet n 8 oki semiconductor [1] for the purpose of this table, rated value is calculated as an average of the lh and hl delay times of each macro type. [2] characteristics are quoted for a typical process. [3] th l (c,d) 3 0.1 ns. for i/o information, please refer to the ac characteristics listed in the i/o table. [1] for the purpose of this table, rated value is calculated as an average of the lh and hl delay times of each macro type [2] characteristics are quoted for a typical process. [3] th l (c,d) 3 0.15 ns. for i/o information, please refer to the ac characteristics listed in the i/o table. ac characteristics (core v dd = 5 v, v ss = 0 v, t j = 25?c) parameter driving type conditions rated value [1][2] unit internal gate delay times inverter 2-input nand 2-input nor 1x 1x 1x input tr/tf = v dd /1.0 ns output loading: fo = 1, l = 0 mm 0.20 0.25 0.28 ns inverter 1x 2x 4x input tr/tf = v dd /1.0 ns output loading: fo = 2, l = 2 mm l = metal length 0.47 0.35 0.22 ns 2-input nand 1x 2x 4x 0.57 0.36 0.25 ns 2-input nor 1x 2x 4x 0.69 0.53 0.51 ns flip-flop (fd1a) delay time: set-up time: hold time: clk - to q d to clk - clk - to d 1.63 1.5 0.1 [3] ns toggle frequency of flip-flop fo = 1, l = 0 mm 500 mhz ac characteristics (core v dd = 3.3 v, v ss = 0 v, t j = 25?c) parameter driving type conditions rated value [1][2] unit internal gate delay times inverter 2-input nand 2-input nor 1x 1x 1x input tr/tf = v dd /1.0 ns output loading: fo = 1, l = 0 mm 0.31 0.38 0.43 ns inverter 1x 2x 4x input tr/tf = v dd /1.0 ns output loading: fo = 2, l = 2 mm l = metal length 0.72 0.54 0.34 ns 2-input nand 1x 2x 4x 0.87 0.55 0.38 ns 2-input nor 1x 2x 4x 1.06 0.81 0.78 ns flip-flop (fd1a) delay time: set-up time: hold time: clk - to q d to clk - clk - to d 2.66 2.29 0.15 [3] ns toggle frequency of flip-flop fo = 1, l = 0 mm 327 mhz
n msm38s/98s data sheet n 9 oki semiconductor [1] rated values are calculated as an average of the l-h and the h-l delay times for each macro type. [2] characteristics are quoted for a typical process. [3] parameters include level shifter cell where appropriate. [4] for l = 2 mm, metal capacitance value of 0.304 pf has been chosen. [5] output rising and falling times are specified. ac characteristics (i/o v dd = 3.3 v or 5 v, v ss = 0 v, t j = 25?c) parameter type conditions rated values for v dd conditon [1][2] unit ll 3-v ext 3-v core hl 3-v ext [3] 5-v core lh 5-v ext [3] 3-v core hh 5-v ext 5-v core input buffer delay times ttl input input tr, tf = 0.2 ns/3.3 v fo = 2, l = 2 mm [4] 0.82 ns cmos input input tr, tf = 0.3 ns/5 v (lh, hh) tr, tf = 0.2 ns/3.3 v (ll, hl) fo = 2, l = 2 mm [4] 0.95 1.78 0.96 0.71 ns output buffer delay times (t in = 0.3 ns/5 v for lh & hl or t in = 0.2 ns/3.3 v for ll & hl) push-pull for hh & lh 4 ma 8 ma 16 ma 24 ma c l = 20 pf c l = 50 pf c l = 100 pf c l = 150 pf 2.90 3.86 3.87 3.69 1.39 1.86 2.03 2.51 ns push-pull for ll & hl 2 ma 4 ma 8 ma 12 ma c l = 20 pf c l = 50 pf c l = 100 pf c l = 150 pf 2.30 3.11 3.34 3.76 1.53 1.99 2.18 2.58 ns output buffer transition time (20-80%) push-pull c l = 150 pf for 24 ma buffer [5] 3.38 (r) 3.59 (f) 2.66 (r) 3.04 (f) ns push-pull with slew rate control 9.20 (r) 7.86 (f) 3.60 (r) 3.62 (f) ns
n msm38s/98s data sheet n 10 oki semiconductor macro library figure 4. oki macro library macrocells for driving clock trees oki offers clock-tree drivers that guarantee a skew time of less than 1.0 ns. the advanced layout software uses dynamic driver placement and sub-trunk allocation to optimize the clock-tree implementation for a particular circuit. features of the clock-tree driver-macrocells include: clock skew 1.0 ns automatic fan-out balancing macro library macrocells basic macrocells basic macrocells w/ scan test clock tree driver macrocells output macrocells msi macrocells mega macrocells input macro- functions bi-directional macro-functions msi macro- functions oscillator macro- functions macro-functions examples nands nors exors flip-flops 3-state outputs push-pull outputs counters shift registers rtc scsi inputs inputs w/pull-ups 74199 74163 gated oscillators latches flip-flops combinational logic open drain outputs slew rate control outputs pci outputs inputs w/pull-downs i/o i/o w/pull-ups i/o w/pull-downs pci i/o 74151 sog rams (single- and multi-port) sog roms uart, 82cxx pci, pcmcia memory macrocells optimized diffused rams (single- and multi-port) optimized diffused roms
n msm38s/98s data sheet n 11 oki semiconductor dynamic sub-trunk allocation single clock tree driver logic symbol single-level clock drivers automatic branch length minimization dynamic driver placement up to four clock trunks the clock-skew management scheme is described in detail in the 0.8? technology clock skew management application note . figure 5. clock tree structure output driver macrocells for slew rate control the slew-rate-control output driver macrocells reduce both simultaneous-switching noise and output- ringing noise. the output transistors are split into two sets; first, one set of output transistors drive the output pads, then, after the output passes the threshold, the second set of output transistors drive the i/o pads. figure 6 below shows output drivers configured for slew-rate control. all outputs with a drive of 8 ma or more are available with slew-rate control. figure 6. slew rate control output buffer clock tree driver macrocell clock drivers sub trunk clocked cell input buffer pad branch main trunk switch output pad second set of output transistors first set of output transistors from internal node
n msm38s/98s data sheet n 12 oki semiconductor automatic test vector generation oki? 0.8 m m asic technologies support automatic test vector generation (atvg) using full scan-path design techniques, including the following: increases fault coverage 3 95% uses synopsys test compiler automatically inserts scan structures connects scan chains traces and reports scan chains checks for rule violations generates complete fault reports allows multiple scan chains supports vector compaction figure 7. full scan path conguration scan data in scan select d c sd ss q qn d c sd ss a b combinational logic fd1as fd1as scan data out q qn
n msm38s/98s data sheet n 13 oki semiconductor design process figure 8. oki design process floorplanning cdc [1] floorplanning scan insertion (optional) cdc [1] fault simulation [5] (cadence verifault or ikos) schematics test vectors vhdl/hdl description test vector conversion (oki tpl [3] ) netlist conversion (edif 200) tdc [2] pre-layout simulation (cadence verilog) layout (silvar lisco gards) automatic test vector generation (synopsys test compiler) verification (cadence dracula) post-layout simulation (cadence verilog) manufacturing prototype test program conversion level 1 [4] level 2 level 2.5 [4] level 3 [4] cae front-end oki interface [1] oki circuit data check program (cdc) verifies logic design rules [2] oki test data check program (tdc) verifies test vector rules [3] oki test pattern language (tpl) [4] alternate customer-oki design interfaces available in addition to standard level 2 [5] standard design process includes fault simulation simulation
n msm38s/98s data sheet n 14 oki semiconductor oki advanced design center cad tools floorplanning for front-end simulation and back-end layout controls clock tree structures improve first-time silicon success by eliminating clock skew problems power calculation which predicts circuit power under simulation conditions to accurately model package requirements [1] contact oki application engineering for current software versions. [2] sun or sun-compatible. [3] in development. design kits vendor platform operating system [1] vendor software [1] description cadence sun [2] sunos solaris [3] composer verilog veritime verifault synergy concept leapfrog design capture simulation timing analysis fault grading design synthesis design capture vhdl simulation hp9000, 7xx hp-ux composer verilog veritime verifault synergy design capture simulation timing analysis fault simulation design synthesis ibm rs6000 aix composer verilog synergy design capture simulation design synthesis ikos sun [2] sunos solaris [3] alchemy simulation fault grading mentor graphics hp9000, 7xx hp-ux idea quickvhdl quicksim ii quickpath quickfault quickgrade autologic dft advisor design capture vhdl simulation logic simulation timing analysis fault grading fault grading design synthesis test synthesis sun [2] sunos solaris [3] synopsys (interface to mentor graphics, viewlogic) sun [2] hp9000, 7xx ibm rs6000 sunos solaris [3] hp-ux aix design compiler hdl/vhdl compiler test compiler vss compilation design synthesis test synthesis vhdl simulation viewlogic sun [2] sunos solaris [3] workview plus powerview vantage optium viewtime/motive [3] viewretargeter viewsynthesis viewsim with vso design capture simulation vhdl simulation timing analysis design migration design synthesis simulation pc dos windows windows nt [3]
n msm38s/98s data sheet n 15 oki semiconductor package options [1] i/o pads can be used for input, output, bidirectional, power, or ground signals. l = available now [1] i/o pads can be used for input, output, bidirectional, power, or ground signals. [2] 1.0mm thick [3] 1.4mm thick l = available now MSM38S0000 42-alloy qfp package menu master slice msm38s... i/o pads [1] qfp (42-alloy) 44 60 80 100 128 136 144 160 0110 100 l l l l 0210 136 l l l 0300 160 l l l l l 0570 216 l l l l 0980 280 l l l l 1500 344 l l 2250 420 l body size (mm) 9.5 x 10.5 15 x 19 14 x 20 14 x 20 28 x 28 28 x 28 28 x 28 28 x 28 lead pitch (mm) 0.8 1 0.8 0.65 0.8 0.65 0.65 0.65 MSM38S0000 cu-alloy qfp and tqfp package menu master slice msm38s... i/o pads [1] qfp (cu-alloy) tqfp 176 208 240 272 304 44 [2] 64 [2] 80 [2] 100 [2] 144 [3] 0110 100 l l l l 0210 136 l l l l l 0300 160 l l l l l 0570 216 l l l l l 0980 280 l l l l 1500 344 l l l l l 2250 420 l l l l l body size (mm) 24 x 24 28 x 28 32 x 32 36 x 36 40 x 40 10 x 10 10 x 10 12 x 12 14 x 14 20 x 20 lead pitch (mm) 0.5 0.5 0.5 0.5 0.5 0.8 0.5 0.5 0.5 0.5
n msm38s/98s data sheet n 16 oki semiconductor [1] i/o pads can be used for input, output, bi-directional, power or ground. l = available now MSM38S0000 plcc and cpga package menu master slice msm38s... i/o pads [1] plcc cpga 44 84 88 132 176 208 401 0110 100 l l 0210 136 l l l l 0300 160 l l l l 0570 216 l l l 0980 280 l l l 1500 344 l l l 2250 420 l l body size (mm) 17x17 28x28 33x33 35x35 38x38 44x44 50x50 lead pitch (mm) 1.27 1.27 2.54 2.54 2.54 2.54 1.27
n msm38s/98s data sheet n 17 oki semiconductor l = available now m = in development [1] i/o pads can be used for input, output, bidirectional, power, or ground connections. msm98s000 qfp package menu master slice msm98s... i/o pads [1] pqfp (42-alloy) pqfp (cu-alloy) tqfp 44 60 80 100 128 136 144 160 176 208 240 272 304 44 64 80 100 020x020 80 m m m m m m 023x023 92 l m m m m l 026x026 104 l m m m l m m l 029x029 116 m m m m l m l l 032x032 128 m m m m l l m m l 035x035 140 m m m m l l m l l m 038x038 152 m m l m l l m l m l 041x041 164 m m l l l l l m m l m 044x044 176 m m m m l l l m m l 047x047 188 m m m l l l l l m l l 050x050 200 m m m m m l l l m l m 053x053 212 m m m m l l l l m m l m 056x056 224 m m m m l l l l m l l l 059x059 236 m m m m l m l l l l m l 062x062 248 m m m l l l l l m m m l 065x065 260 m m m m l l l l m l m m l 068x068 272 m m m m m l l l l l l m m 071x071 284 l l l l m m m 074x074 296 l l l l m m m 077x077 308 l l l l m l m 080x080 320 l l l l m l m 083x083 332 l l l l m l m 086x086 344 m m l m l l l l 089x089 356 m l m m l l l m 092x092 368 l l l m m l l m 095x095 380 l m l l m l m m 098x098 392 l m l l m m m m 101x101 404 m l m l m m m m 104x104 416 m l m l l l m l l body size 9.5 x 10.5 15 x 19 14 x 20 14 x 20 28 x 28 28 x 28 28 x 28 28 x 28 28 x 28 24 x 24 32 x 32 36 x 36 40 x 40 10 x 10 10 x 10 12 x 12 14 x 14 lead pitch (mm) 0.8 1 0.8 0.65 0.8 0.65 0.65 0.65 0.5 0.5 0.5 0.5 0.5 0.8 0.5 0.5 0.5
n msm38s/98s data sheet n 18 oki semiconductor l = available now m = in development [1] i/o pads can be used for input, output, bidirectional, power, or ground signals. msm98s000 plcc and cpga package menu master slice msm98s... i/o pads [1] plcc cpga 44 84 72 88 132 176 208 020x020 80 m m 023x023 92 m m m 026x026 104 m m m 029x029 116 l l m l 032x032 128 l l m l m 035x035 140 l l m l m 038x038 152 l m l m 041x041 164 l m l m 044x044 176 l m l l 047x047 188 l m l l m 050x050 200 l l l l m 053x053 212 l l l l m 056x056 224 l l m l m m 059x059 236 l l m l m m 062x062 248 l l m l m m 065x065 260 l l m l m m 068x068 272 l l m l l m 071x071 284 l l m l l m 074x074 296 l m l l m 077x077 308 m m l l m 080x080 320 m m l l l 083x083 332 m m l l l 086x086 344 m m l l l 089x089 356 m m l l l 092x092 368 m m l l l 095x095 380 m m l l l 098x098 392 m m l m l 101x101 404 m m l m l 104x104 416 m m l m l body size 17 x 17 28 x 28 28 x 28 33 x 33 35 x 35 38 x 38 44 x 44 lead pitch (mm) 1.27 1.27 2.54 2.54 2.54 2.54 2.54
n msm38s/98s data sheet n 19 oki semiconductor
n msm38s/98s data sheet n 20 oki semiconductor
northwest area 785 n. mary avenue sunnyvale, ca 94086 tel: 408/720-8940 fax: 408/720-8965 southwest area 2302 martin street suite 250 irvine, ca 92715 tel: 714/752-1843 fax: 714/752-2423 central area 2007 n. collins blvd. suite 303 richardson, tx 75080 tel: 214/690-6868 fax: 214/690-8233 southeast area 1590 adamson parkway suite 220 morrow, ga 30260 tel: 404/960-9660 fax: 404/960-9682 eastern area shattuck office center 138 river road andover, ma 01810 tel: 508/688-8687 fax: 508/688-8896 automotive electronics 17177 n. laurel park drive suite 433 livonia, mi 48152 tel: 313/464-7200 fax: 313/464-1724 corporate headquarters 785 n. mary avenue sunnyvale, ca 94086-2909 tel: 408/720-1900 fax: 408/720-1918 for oki literature: call toll free 1-800-oki-6388 (6 a.m. to 5 p.m. pacific time) oki stock no: 010400-002 oki r egional s ales o ffices

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